Fundamentals of computer organisation and architecture

The internal components of a computer normally include CPU, components within a CPU, main memory, buses and I/O controllers. The following block diagram shows how different components of a computer working together as a functional system.

Objective: understand the role of the following components and how they relate to each other:

• Processor

  The processor is made up by the control unit, the arithemetic logic unit(ALU) and several registers.

• The control unit
  • The control unit controls and coordinates all operations.
  • It works through a cycle of fetch, decode, and execution.
    • fetch operation fetches the next instruction from the main memeory
    • decode operation outputs what the ALU needs to perform on the data
    • execution operation causes the instruction to be carried out
  • The role of control unit can be summarised as below:
    • To fetch / decode / execute instructions;
    • To synchronise operation of processor;
    • To marshal/control operation of fetch-execute cycle;
    • To send control signals/commands to other components of fetch-execute cycle;
• Registers
  • Registers are small but very fast memory to hold data before and after being processed by the CPU.
  • All ALU operations are accomplished within registers.
• ALU

  ALU performs addition, subtraction, multiplication, division, comparison(logical ops), and bitwise operations (more later).

• Memory
  • Memory is used to hold temporary instructions and data for manipulation while the system is running.
  • When a block of code or data that is held in memory, it is directly accessible to the CPU for manipulation.
  • Memory is organised in units called words. A word is the maximum number of bits a CPU can process in a single instruction. Typical word size are 8, 16, 32, or 64 bits.
  • Each word has its own address in the memory.

Objectives: Understand the need for, and means of, communication between components. In particular, understand the concept of a bus and how address, data and control buses are used.

Components communicate with each other using buses. A bus is a set of parallel wires connecting different coomponents. The processor is connected to the main memory by three separate buses. The three types of buses:

• Address bus
  • Address bus is a pathway or a set of parallel wires that carries the location of the data to be read from or written to. An address bus is one directional only - from the processor to the memory or an I/O controller.
  • The number of lines for the address bus determines the maximum number of bits it can carry, and in turn determines the maximum possible memory capacity of the computer. To understand this, think if the postal office only allows 3 digits for house numbers, then the maximum addressable houses will be 999. So, if the computer has a 32-bit bus, the maximum addressable memory locations will be 2³², which is 4GB, assuming each memory location stores on byte of data.
• Data bus
  • Data bus is a bi-directional pathway or wires that carries data or instructions between computer components.
  • The width of data bus is a key factor in determining the overall computer performance. Typical data bus is 8, 16, 32 or 64 bits wide. If a computer has a word size of 32 but with a 16-bit data bus, then the data bus has to fetch the word twice from the main memory.
• Control bus
  • Control bus is a bi-directional pathway that carries command, timing and specific status information among components. The following are some of the control information a control bus may carry:
    • write to memory
    • read from memory
    • write to I/O port
    • read from I/O port
    • request for data bus
    • grant for data bus
    • sync clock
    • reset all components

• I/O controllers
  • An I/O conyroller is a device (an electronic circuit board) that manages the communication between the processor and the I/O device.
  • Each I/O device has a separate controller which connects to the control bus.
  • I/O controllers receive input and output requests from the pocessor, then send device specific control signals to the device.
  • I/O controllers manage the data flow from and to the device.

Objectives: Be able to explain the difference between von Neumann and Harvard architectures and describe where each is typically used.

• arithmetic logic unit: A circuit inside a CPU performs the following functions:
  • ADD, SUBTRACT, MULTIPLY, DIVIDE
  • Arithmetic(signed bit patterns) and logic shift(unsigned bit patterns) on instructions within a register
  • Performs logical operations such as AND, XOR, OR, NOT.
• control unit:
  • It controls and coordinates the activities within the CPU and control the flow of data in and out of CPU.
  • It takes an instruction and decodes it into opcode and operands.
  • It manages the execution of the decoded instrcutions, fetches data from location and stores the resultst in memory or registers.
• clock:
  • The system clock is used to synchronise CPU operations.
  • It generates series of signals of alternating 0 and 1.
  • The CPU takes at least one cycle of time (from 0 to 1 or from 1 to 0) to perform one instruction.
• general-purpose registers:
  • Registers are very fast and small memory inside CPU to hold data before, during and after being processed by the CPU
  • Typically, a CPU can have up to 16 registers
  • Some CPUs only have one general purpose register, called accumulator.
• dedicated registers, including:
  • program counter(PC): a special purpose register that holds the address of the next instruction.
  • current instruction register(CIR or IR): holds the currently being executed instruction.
  • memory address register(MAR): holds the memory address to be fetched from or written to.
  • memory buffer register(MBR): a.k.a. memory data register(MDR), holds the data fetched from or written to memory.
  • status register(SR): holds the bits to indicate the results of the execution of an instruction, such as oervflow, negative, zero or carry over.

When each instruction of a program is being processed by the CPU, it goes through the cycle of three stages:

1. fetching: retrieves a program instruction from its memory
2. decoding: determines what actions the instruction requires
3. executing: carries out the decoded actions

Registers' roles in the fetch-decode-execution cycle can be illustrated in the following flowchart.(You should get familar with the flowchart).

Fetch:

• contents of PC transferred to MAR. MAR<-[PC]
• address bus used to transfer this address to main memory
• contents of addressed memory location moved into the MBR by the data bus, while incrementing PC. MBR<-[Memory]MARaddress; PC<-[PC]+1
• transfer MBR to CIR, ready to be decoded. CIR<-[MBR]

Decode:

• decode instruction held by the CIR by the control unit. decode [CIR]
• instruction split into opcode and operand

Execute:

• if necessary,data is fetched
• the opcode identifies the instruction to execute
• execute instruction by relevant part of processor
• result stored in accumulator
• status register is updated

Click the play button for step-by-step animation of the cycle:

Here is another resource to help you:

• Processor instruction set means “all the instructions supported by its hardware”
• different processors have different instruction sets
• typical instruction set includes the following common operations:
  • LOAD, STORE - data handling and memory operations
  • ADD, SUBTRACT, DIVID, MULTIPLY etc - arithmetic operations
  • >, <, = etc - comparison operations
  • AND, OR, XOR, NOR, NOT etc - logical operations
  • Control flow operations - conditional or unconditional
  • Logical shifts
  • Halt

• machine instruction is made of two parts:
  • opcode: the operation to be performed, and a 2-bit code indicate addressing mode used for the operation
  • operands: the value, memory address or register to be operated on

• machine instruction is made of two parts:
  • opcode: the operation to be performed
  • a 2-bit code indicate addressing mode used for the operation
• addressing modes
  • immediate addressing: the operand is the actual value to be operated on.
  • direct addressing: the operand holds the memory address of the value to be operated on.

Suppose that the opcode 010 means LOAD and the addressing mode 1 indicates direct addressing.
Describe the operation that will be performed by the following machine code instruction:
0101 1100

The above instruction means: LOAD the value from the memory location at 12.